[all-commits] [llvm/llvm-project] b663f3: [RISCV] Prevent formation of shXadd(.uw) and add.u...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b663f30fa45ce86c8a3362624b87ccb372bd036a
      https://github.com/llvm/llvm-project/commit/b663f30fa45ce86c8a3362624b87ccb372bd036a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-19 (Sat, 19 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi.

If the outer add has an simm12 immediate operand we should prefer
it instead of materializing it in a register. This would guarantee
and extra instruction and temporary register. Since we don't check
one use on the shl or zext we might generate more instructions if
there is an additional user.