[all-commits] [llvm/llvm-project] ac8713: [RISCV] Teach vsetvli insertion to remember when p...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac87133f1de902bcc7ab4330e7ac79b2ba376d34
      https://github.com/llvm/llvm-project/commit/ac87133f1de902bcc7ab4330e7ac79b2ba376d34
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-18 (Fri, 18 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

  Log Message:
  -----------
  [RISCV] Teach vsetvli insertion to remember when predecessors have same AVL and SEW/LMUL ratio if their VTYPEs otherwise mismatch.

Previously we went directly to unknown state on VTYPE mismatch.
If we instead remember the partial match, we can use this to
still use X0, X0 vsetvli in successors if AVL and needed SEW/LMUL
ratio match.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D104069