[all-commits] [llvm/llvm-project] 78b75b: [AArch64] Add TableGen patterns to generate uaddlv

[JinGu Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78b75b452b08e4ce3ad468e426e6e4fa1c92f7bd
      https://github.com/llvm/llvm-project/commit/78b75b452b08e4ce3ad468e426e6e4fa1c92f7bd
  Author: Jingu Kang <jingu.kang at arm.com>
  Date:   2021-06-18 (Fri, 18 Jun 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-vabs.ll
    M llvm/test/CodeGen/AArch64/neon-sad.ll
    A llvm/test/CodeGen/AArch64/neon-uaddlv.ll

  Log Message:
  -----------
  [AArch64] Add TableGen patterns to generate uaddlv

uaddv(uaddlp(x)) ==> uaddlv(x)
addp(uaddlp(x))  ==> uaddlv(x)

Differential Revision: https://reviews.llvm.org/D104236