[all-commits] [llvm/llvm-project] 6f0e74: Avoid unnecessary AArch64 DSB in __clear_cache in ...

[Kristof Beyls via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f0e74cd583ba6fbb897d3ab16a9b75e91484275
      https://github.com/llvm/llvm-project/commit/6f0e74cd583ba6fbb897d3ab16a9b75e91484275
  Author: Kristof Beyls <kristof.beyls at arm.com>
  Date:   2021-06-17 (Thu, 17 Jun 2021)

  Changed paths:
    M compiler-rt/lib/builtins/clear_cache.c

  Log Message:
  -----------
  Avoid unnecessary AArch64 DSB in __clear_cache in some situations.

The dsb after instruction cache invalidation only needs to be executed
if any instruction cache invalidation did happen.
Without this change, if the CTR_EL0.DIC bit indicates that instruction
cache invalidation is not needed, __clear_cache would execute two dsb
instructions in a row; with the second one being unnecessary.

Differential Revision: https://reviews.llvm.org/D104371