[all-commits] [llvm/llvm-project] 1c450c: [PowerPC] Export 16 byte load-store instructions

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c450c3d7ec01d9daaf9f2651da93b01e7790ffd
      https://github.com/llvm/llvm-project/commit/1c450c3d7ec01d9daaf9f2651da93b01e7790ffd
  Author: Kai Luo <lkail at cn.ibm.com>
  Date:   2021-06-15 (Tue, 15 Jun 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
    M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
    M llvm/lib/Target/PowerPC/PPCInstrFormats.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.h
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    M llvm/lib/Target/PowerPC/PPCSchedule.td
    A llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
    A llvm/test/CodeGen/PowerPC/ldst-16-byte.mir
    M llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
    M llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
    M llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
    M llvm/test/MC/PowerPC/ppc64-encoding.s

  Log Message:
  -----------
  [PowerPC] Export 16 byte load-store instructions

Export `lq`, `stq`, `lqarx` and `stqcx.` in preparation for implementing 16-byte lock free atomic operations on AIX.
Add a new register class `g8prc` for these instructions, since these instructions require even-odd register pair.

Reviewed By: nemanjai, jsji, #powerpc

Differential Revision: https://reviews.llvm.org/D103010