[all-commits] [llvm/llvm-project] c75e45: [RISCV] Transform unaligned RVV vector loads/store...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c75e454cb93206833f8cedde1ed5d12ef161e357
      https://github.com/llvm/llvm-project/commit/c75e454cb93206833f8cedde1ed5d12ef161e357
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-06-14 (Mon, 14 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    A llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

  Log Message:
  -----------
  [RISCV] Transform unaligned RVV vector loads/stores to aligned ones

This patch adds support for loading and storing unaligned vectors via an
equivalently-sized i8 vector type, which has support in the RVV
specification for byte-aligned access.

This offers a more optimal path for handling of unaligned fixed-length
vector accesses, which are currently scalarized. It also prevents
crashing when `LegalizeDAG` sees an unaligned scalable-vector load/store
operation.

Future work could be to investigate loading/storing via the largest
vector element type for the given alignment, in case that would be more
optimal on hardware. For instance, a 4-byte-aligned nxv2i64 vector load
could loaded as nxv4i32 instead of as nxv16i8.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D104032