[all-commits] [llvm/llvm-project] 08ce52: [AArch64] Improve SAD pattern

[JinGu Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 08ce52ef5e6b879216f8018b920ef5c0621e797d
      https://github.com/llvm/llvm-project/commit/08ce52ef5e6b879216f8018b920ef5c0621e797d
  Author: Jingu Kang <jingu.kang at arm.com>
  Date:   2021-06-14 (Mon, 14 Jun 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-vabs.ll
    M llvm/test/CodeGen/AArch64/neon-sad.ll

  Log Message:
  -----------
  [AArch64] Improve SAD pattern

Given a vecreduce_add node, detect the below pattern and convert it to the node
sequence with UABDL, [S|U]ADB and UADDLP.

i32 vecreduce_add(
 v16i32 abs(
   v16i32 sub(
    v16i32 [sign|zero]_extend(v16i8 a), v16i32 [sign|zero]_extend(v16i8 b))))
=================>
i32 vecreduce_add(
  v4i32 UADDLP(
    v8i16 add(
      v8i16 zext(
        v8i8 [S|U]ABD low8:v16i8 a, low8:v16i8 b
      v8i16 zext(
        v8i8 [S|U]ABD high8:v16i8 a, high8:v16i8 b

Differential Revision: https://reviews.llvm.org/D104042