[all-commits] [llvm/llvm-project] 645541: [compiler-rt] [builtins] [AArch64] Add missing AAr...

[stephenhines via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6455418d3d2a2de1a8251cc2ccf2e87b9ae3112d
      https://github.com/llvm/llvm-project/commit/6455418d3d2a2de1a8251cc2ccf2e87b9ae3112d
  Author: Stephen Hines <srhines at google.com>
  Date:   2021-06-11 (Fri, 11 Jun 2021)

  Changed paths:
    M compiler-rt/lib/builtins/clear_cache.c

  Log Message:
  -----------
  [compiler-rt] [builtins] [AArch64] Add missing AArch64 data synchronization barrier (dsb) to __clear_cache

https://developer.arm.com/documentation/den0024/a/Caches/Cache-maintenance
covers how to properly clear caches on AArch64, and the builtin
implementation was missing a `dsb ish` after clearing the icache for the
selected range.

Reviewed By: kristof.beyls

Differential Revision: https://reviews.llvm.org/D104094