[all-commits] [llvm/llvm-project] bc104f: [PowerPC] Relax register superclasses for paired m...

[Qiu Chaofan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bc104fdcecc0da1650177f3587ffe233b37f071b
      https://github.com/llvm/llvm-project/commit/bc104fdcecc0da1650177f3587ffe233b37f071b
  Author: Qiu Chaofan <qiucofan at cn.ibm.com>
  Date:   2021-06-11 (Fri, 11 Jun 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll
    M llvm/test/CodeGen/PowerPC/constant-pool.ll
    M llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
    M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/mma-outer-product.ll
    M llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
    M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/remove-redundant-moves.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vsx.ll

  Log Message:
  -----------
  [PowerPC] Relax register superclasses for paired memops

Relaxing superclass constraint for VSX register classes helps reducing
32-byte spills and copies when register pressure is high.

In test case affected, some of them introduces more copies due to new
allocation order. However, this patch should not be the root cause, and
we may be able to fix it in other places of register allocation.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D104006