[all-commits] [llvm/llvm-project] 420bd5: [RISCV] Use ComputeNumSignBits/MaskedValueIsZero i...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 420bd5ee8ec996a2c2e305541e59465a5ba436e3
      https://github.com/llvm/llvm-project/commit/420bd5ee8ec996a2c2e305541e59465a5ba436e3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-10 (Thu, 10 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/rem.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.

This helps us select W instructions in more cases. Most of the
affected tests have had the sign_extend_inreg or AND folded into
sextload/zextload.

Differential Revision: https://reviews.llvm.org/D104079