[all-commits] [llvm/llvm-project] 119965: LoadStoreVectorizer: support different operand ord...

[Volkan Keles via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 119965865cc730060e4cc95690ee7dab91c2c440
      https://github.com/llvm/llvm-project/commit/119965865cc730060e4cc95690ee7dab91c2c440
  Author: Slava Nikolaev <vnikolaev at apple.com>
  Date:   2021-06-10 (Thu, 10 Jun 2021)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
    M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll

  Log Message:
  -----------
  LoadStoreVectorizer: support different operand orders in the add sequence match

First we refactor the code which does no wrapping add sequences
match: we need to allow different operand orders for
the key add instructions involved in the match.

Then we use the refactored code trying 4 variants of matching operands.

Originally the code relied on the fact that the matching operands
of the two last add instructions of memory index calculations
had the same LHS argument. But which operand is the same
in the two instructions is actually not essential, so now we allow
that to be any of LHS or RHS of each of the two instructions.
This increases the chances of vectorization to happen.

Reviewed By: volkan

Differential Revision: https://reviews.llvm.org/D103912