[all-commits] [llvm/llvm-project] 933df6: [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_C...

[Jessica Paquette via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 933df6ca796c0ace889bcc64706ec53462bd859a
      https://github.com/llvm/llvm-project/commit/933df6ca796c0ace889bcc64706ec53462bd859a
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2021-06-10 (Thu, 10 Jun 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
    A llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF

This adds legalization for scalar G_CTTZ and G_CTTZ_ZERO_UNDEF. Vector support
requires handling vector G_BITREVERSE, which I haven't gotten around to yet.

For G_CTTZ_ZERO_UNDEF, we just lower it to G_CTTZ.

For G_CTTZ, we match SelectionDAG's lowering to a G_BITREVERSE + G_CTLZ.

e.g. https://godbolt.org/z/nPEseYh1s

(With this patch, we have slightly worse codegen than SDAG for types smaller
than s32; it seems like we're missing a combine.)

Also, this adds in a function to build G_BITREVERSE to MachineIRBuilder.

Differential Revision: https://reviews.llvm.org/D104065