[all-commits] [llvm/llvm-project] 96ca2d: [mlir][ArmSVE] Add basic load/store operations

[jsetoain via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 96ca2d92b52bd97fcdce4c0ba2723399b005e0a9
      https://github.com/llvm/llvm-project/commit/96ca2d92b52bd97fcdce4c0ba2723399b005e0a9
  Author: Javier Setoain <javier.setoain at gmail.com>
  Date:   2021-06-09 (Wed, 09 Jun 2021)

  Changed paths:
    M mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td
    M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
    A mlir/test/Dialect/ArmSVE/memcpy.mlir
    M mlir/test/Dialect/ArmSVE/roundtrip.mlir
    M mlir/test/Target/LLVMIR/arm-sve.mlir

  Log Message:
  -----------
  [mlir][ArmSVE] Add basic load/store operations

ArmSVE-specific memory operations are needed to generate end-to-end
code for as long as MLIR core doesn't support scalable vectors. This
instructions will be eventually unnecessary, for now they're required
for more complex testing.

Differential Revision: https://reviews.llvm.org/D103535