[all-commits] [llvm/llvm-project] 8b4c80: Further improve register allocation for vwadd(u).w...
Craig Topper via All-commits
all-commits at lists.llvm.org
Tue Jun 8 09:44:05 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 8b4c80d380a681e6ea6ea60e9d9f9424e7782980
https://github.com/llvm/llvm-project/commit/8b4c80d380a681e6ea6ea60e9d9f9424e7782980
Author: Craig Topper <craig.topper at sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
Log Message:
-----------
Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.
The first source has the same EEW as the destination, but we're
using earlyclobber which prevents them from ever being the same
register. This patch attempts to work around this.
-For unmasked .wv, add a special TIED pseudo that pretends like
the first operand and the destination must be the same register. This
disables the earlyclobber for that source. Mark the instruction
as convertible to 3 address form which will switch it to the
original untied pseudo when the TwoAddressInstructionPass decides
that keeping them tied would require an extra copy. This uses
code in RISCVInstrInfo.cpp to do the conversion to the untied
opcode.
The untie test case show that we can generate the untied version.
Not sure it was profitable to do it in this case, but they have
really simple IR.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D103552
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