[all-commits] [llvm/llvm-project] c57bce: [RISCV] Remove ForceTailAgnostic flag from vmv.s.x...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c57bce9cc5facbdde52c24fe64fa4f6bf23a8449
      https://github.com/llvm/llvm-project/commit/c57bce9cc5facbdde52c24fe64fa4f6bf23a8449
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-08 (Tue, 08 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions.

In 0.9 these were defined to leave elements other than 0 in the
destination unmodified. They were changed to use the tail policy
in 0.10. I missed that update.

I assume no one has noticed because in order cores treat tail
agnostic the same as tail undisturbed. I believe Spike and QEMU do
the same.

Reviewed By: arcbbb, frasercrmck

Differential Revision: https://reviews.llvm.org/D103736