[all-commits] [llvm/llvm-project] f8816c: [AMDGPU] Add v5f32/VReg_160 support for MIMG instr...

[Carl Ritson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f8816c7400250961af4810956248c3636a5fcb04
      https://github.com/llvm/llvm-project/commit/f8816c7400250961af4810956248c3636a5fcb04
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2021-06-08 (Tue, 08 Jun 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/MIMGInstructions.td
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.o.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
    M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
    M llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
    M llvm/test/MC/Disassembler/AMDGPU/mimg_gfx10.txt

  Log Message:
  -----------
  [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions

Avoid having to round up to v8f32/VReg_256 when only 5 VGPRs are
required for a MIMG address operand.

Maintain _V8 instruction variants of pseudo instructions allowing
assembly prior to GFX10 to work as-is.  Currently the validator
can tell for GFX10 what the correct size is, so will disallow
oversize address registers.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D103672