[all-commits] [llvm/llvm-project] f30f8b: [RISCV] Lower i8/i16 bswap/bitreverse to grevi/gre...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f30f8b4f12b762a054800aaa7b60461fd177fa96
      https://github.com/llvm/llvm-project/commit/f30f8b4f12b762a054800aaa7b60461fd177fa96
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-07 (Mon, 07 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv32zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll

  Log Message:
  -----------
  [RISCV] Lower i8/i16 bswap/bitreverse to grevi/greviw with Zbp.

Include known bits support so we know we don't need to zext the
output if the input was already zero extended.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D103757