[all-commits] [llvm/llvm-project] 0b3b0a: [AArch64][RISCV] Make sure isel correctly honors f...

[Eli Friedman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0b3b0a727ad6bac089a57e3625dd9dbf4e6f5bde
      https://github.com/llvm/llvm-project/commit/0b3b0a727ad6bac089a57e3625dd9dbf4e6f5bde
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2021-05-28 (Fri, 28 May 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
    M llvm/include/llvm/CodeGen/MachineMemOperand.h
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
    M llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/utils/TableGen/CodeGenDAGPatterns.cpp

  Log Message:
  -----------
  [AArch64][RISCV] Make sure isel correctly honors failure orderings.

If a cmpxchg specifies acquire or seq_cst on failure, make sure we
generate code consistent with that ordering even if the success ordering
is not acquire/seq_cst.

At one point, it was ambiguous whether this sort of construct was valid,
but the C++ standad and LLVM now accept arbitrary combinations of
success/failure orderings.

This doesn't address the corresponding issue in AtomicExpand. (This was
reported as https://bugs.llvm.org/show_bug.cgi?id=33332 .)

Fixes https://bugs.llvm.org/show_bug.cgi?id=50512.

Differential Revision: https://reviews.llvm.org/D103284