[all-commits] [llvm/llvm-project] b5f8ac: [X86] Pre-commit tests for D103192. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b5f8ac26829385d98f730c2a76c5f9a6306df2f8
      https://github.com/llvm/llvm-project/commit/b5f8ac26829385d98f730c2a76c5f9a6306df2f8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-05-27 (Thu, 27 May 2021)

  Changed paths:
    M llvm/test/CodeGen/X86/vec_shift5.ll

  Log Message:
  -----------
  [X86] Pre-commit tests for D103192. NFC


  Commit: a105d3024efec365961e940c489c4ed5198736d2
      https://github.com/llvm/llvm-project/commit/a105d3024efec365961e940c489c4ed5198736d2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-05-27 (Thu, 27 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vec_shift5.ll

  Log Message:
  -----------
  [X86] Fold (shift undef, X)->0 for vector shifts by immediate.

We could previously do this by accident through the later
call to getTargetConstantBitsFromNode I think, but that only worked
if N0 had a single use. This patch makes it explicit for undef and
doesn't have a use count check.

I think this is needed to move the (shl X, 1)->(add X, X)
fold to isel for PR50468. We need to be sure X won't be IMPLICIT_DEF
which might prevent the same vreg from being used for both operands.

Differential Revision: https://reviews.llvm.org/D103192


Compare: https://github.com/llvm/llvm-project/compare/39957aa4243c...a105d3024efe