[all-commits] [llvm/llvm-project] b44007: [mlir][gpu] Relax restriction on MMA store op to a...

[Thomas via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b44007bec2470db0d9f100c6a9216d8e05cef608
      https://github.com/llvm/llvm-project/commit/b44007bec2470db0d9f100c6a9216d8e05cef608
  Author: thomasraoux <thomasraoux at google.com>
  Date:   2021-05-27 (Thu, 27 May 2021)

  Changed paths:
    M mlir/include/mlir/Dialect/GPU/GPUDialect.h
    M mlir/include/mlir/Dialect/GPU/GPUOps.td
    M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
    M mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp
    M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
    M mlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir
    M mlir/test/Dialect/GPU/invalid.mlir
    M mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir
    M mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir

  Log Message:
  -----------
  [mlir][gpu] Relax restriction on MMA store op to allow chain of mma ops.

In order to allow large matmul operations using the MMA ops we need to chain
operations this is not possible unless "DOp" and "COp" type have matching
layout so remove the "DOp" layout and force accumulator and result type to
match.
Added a test for the case where the MMA value is accumulated.

Differential Revision: https://reviews.llvm.org/D103023