[all-commits] [llvm/llvm-project] e89270: GlobalISel: Do not change register types in lowerLoad

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e892705d74c7366a1404a3b3471001edaa7659f8
      https://github.com/llvm/llvm-project/commit/e892705d74c7366a1404a3b3471001edaa7659f8
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-05-27 (Thu, 27 May 2021)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir

  Log Message:
  -----------
  GlobalISel: Do not change register types in lowerLoad

Adjusting the load register type is a widenScalar type action, not a
lowering. lowerLoad should be reserved for operations that change the
memory access size, such as unaligned load decomposition. With this
trying to adjust the register type, it was hard to avoid infinite
loops in the legalizer. Adds a bandaid to avoid regressing a few
AArch64 tests, but I'm not sure what the exact condition is and
there's probably a cleaner way to do this.

For AMDGPU this regresses handling of some cases for unaligned loads,
but the way this is currently working is a pretty ugly hack.