[all-commits] [llvm/llvm-project] 8c73a3: [RISCV] Allow passing fixed-length vectors via the...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8c73a31c1175cc9dc8de9f056e10d557e470c10b
      https://github.com/llvm/llvm-project/commit/8c73a31c1175cc9dc8de9f056e10d557e470c10b
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-05-27 (Thu, 27 May 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    A llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll

  Log Message:
  -----------
  [RISCV] Allow passing fixed-length vectors via the stack

The vector calling convention dictates that when the vector argument
registers are exhaused, GPRs are used to pass the address via the stack.
When the GPRs themselves are exhausted, at best we would previously
crash with an assertion, and at worst we'd generate incorrect code.

This patch addresses this issue by passing fixed-length vectors via the
stack with their full fixed-length size and aligned to their element
type size. Since the calling convention lowering can't yet handle
scalable vector types, this patch adds a fatal error to make it clear
that we are lacking in this regard.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D102422