[all-commits] [llvm/llvm-project] 772b58: [SelectionDAG][RISCV] Don't unroll 0/1-type bool V...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 772b58a641affcd786e3062250a0f51acb8b1553
      https://github.com/llvm/llvm-project/commit/772b58a641affcd786e3062250a0f51acb8b1553
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-05-27 (Thu, 27 May 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    A llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV] Don't unroll 0/1-type bool VSELECTs

This patch extends the cases in which the legalizer is able to express
VSELECT in terms of XOR/AND/OR. When dealing with a VSELECT between
boolean vector types, the mask itself is an all-ones or all-ones value
of the operand type, so a 0/1 boolean type behaves identically to a 0/-1
type.

This greatly helps RISC-V which relies on expansion for these nodes. It
also allows scalable-vector bool VSELECTs to use the default expansion,
where before it would crash in SelectionDAG::UnrollVectorOp.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103147