[all-commits] [llvm/llvm-project] b2c7ac: [RISCV] Don't propagate VL/VTYPE across inline ass...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b2c7ac874f516df38968d02636ecab7730ca9323
      https://github.com/llvm/llvm-project/commit/b2c7ac874f516df38968d02636ecab7730ca9323
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

  Log Message:
  -----------
  [RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI pass.

It's conceivable someone could put a vsetvli in inline assembly
so its safer to consider them as barriers. The alternative would
be to trust that the user marks VL and VTYPE registers as clobbers
of the inline assembly if they do that, but hat seems error prone.

I'm assuming inline assembly in vector code is going to be rare.

Reviewed By: frasercrmck, HsiangKai

Differential Revision: https://reviews.llvm.org/D103126