[all-commits] [llvm/llvm-project] 8ac66d: [AArch64] Generate LD1 for anyext i8 or i16 vector...

[Andrew Savonichev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8ac66d61eab3dd44defa5755b884eca71a19431c
      https://github.com/llvm/llvm-project/commit/8ac66d61eab3dd44defa5755b884eca71a19431c
  Author: Andrew Savonichev <andrew.savonichev at gmail.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
    M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

  Log Message:
  -----------
  [AArch64] Generate LD1 for anyext i8 or i16 vector load

The existing LD1 patterns do not cover cases where result type does
not match the memory type. This happens when illegal vector types are
extended and scalarized, for example:

  load <2 x i16>* %v2i16

is lowered into:

  // first element
  (v4i32 (insert_subvector (v2i32 (scalar_to_vector (load anyext from i16)))))
  // other elements
  (v4i32 (insert_vector_elt (i32 (load anyext from i16)) idx))

Before this patch these patterns were compiled into LDR + INS.
Now they are compiled into LD1.

The problem was reported in
PR24820: LLVM Generates abysmal code in simple situation.

Differential Revision: https://reviews.llvm.org/D102938