[all-commits] [llvm/llvm-project] bf3b6c: [llvm][sve] Lowering for VLS MLOAD/MSTORE

[David Truby via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bf3b6cf9208166cc5a2980f56265d8123f0e09bf
      https://github.com/llvm/llvm-project/commit/bf3b6cf9208166cc5a2980f56265d8123f0e09bf
  Author: David Truby <david.truby at arm.com>
  Date:   2021-05-20 (Thu, 20 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    A llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll

  Log Message:
  -----------
  [llvm][sve] Lowering for VLS MLOAD/MSTORE

This adds custom lowering for the MLOAD and MSTORE ISD nodes when
passed fixed length vectors in SVE. This is done by converting the
vectors to VLA vectors and using the VLA code generation.

Fixed length extending loads and truncating stores currently produce
correct code, but do not use the built in extend/truncate in the
load and store instructions. This will be fixed in a future patch.

Differential Revision: https://reviews.llvm.org/D101834