[all-commits] [llvm/llvm-project] a64710: [AArch64] Combine vector shift instructions in Sel...

[Andrew Savonichev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a647100b4320923b0e9d156cc3872b3be470ad98
      https://github.com/llvm/llvm-project/commit/a647100b4320923b0e9d156cc3872b3be470ad98
  Author: Andrew Savonichev <andrew.savonichev at gmail.com>
  Date:   2021-05-20 (Thu, 20 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    A llvm/test/CodeGen/AArch64/aarch64-bswap-ext.ll

  Log Message:
  -----------
  [AArch64] Combine vector shift instructions in SelectionDAG

bswap.v2i16 + sitofp in LLVM IR generate a sequence of:

  - REV32 + USHR for bswap.v2i16
  - SHL + SSHR + SCVTF for sext to v2i32 and scvt

The shift instructions are excessive as noted in PR24820, and they can
be optimized to just SSHR.

Differential Revision: https://reviews.llvm.org/D102333