[all-commits] [llvm/llvm-project] 175bdf: [RISCV] Fix operand order in fixed-length VM(OR|AN...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 175bdf127d5bb09c81fbd3dc1e766e4ef26793d0
      https://github.com/llvm/llvm-project/commit/175bdf127d5bb09c81fbd3dc1e766e4ef26793d0
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-05-18 (Tue, 18 May 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll

  Log Message:
  -----------
  [RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns

Where the RVV specification writes `vs2, vs1`, our TableGen patterns use
`rs1, rs2`. These differences can easily cause confusion. The VMANDNOT
instruction performs `LHS && !RHS`, and similarly for VMORNOT.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D102606