[all-commits] [llvm/llvm-project] 339d0c: [InstCombine] add test for shl demanded bits misco...

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 339d0c1d26b638c54abe98aff81e4b00b3549023
      https://github.com/llvm/llvm-project/commit/339d0c1d26b638c54abe98aff81e4b00b3549023
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-05-14 (Fri, 14 May 2021)

  Changed paths:
    M llvm/test/Transforms/InstCombine/shl-demand.ll

  Log Message:
  -----------
  [InstCombine] add test for shl demanded bits miscompile; NFC

PR50341


  Commit: e82db87fb102f01b0895b074e56568025c659575
      https://github.com/llvm/llvm-project/commit/e82db87fb102f01b0895b074e56568025c659575
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-05-14 (Fri, 14 May 2021)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/shl-demand.ll

  Log Message:
  -----------
  [InstCombine] drop poison flags when simplifying 'shl' based on demanded bits

As with other transforms in demanded bits, we must be careful not to
wrongly propagate nsw/nuw if we are reducing values leading up to the shift.

This bug was introduced with 1b24f35f843c and leads to the miscompile
shown in:
https://llvm.org/PR50341


Compare: https://github.com/llvm/llvm-project/compare/6fb02596a209...e82db87fb102