[all-commits] [llvm/llvm-project] 90ffcb: [AArch64][SVE] Add unpredicated vector BIC ISD node

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 90ffcb124566eba54e50ff29f479a6adcd726ae4
      https://github.com/llvm/llvm-project/commit/90ffcb124566eba54e50ff29f479a6adcd726ae4
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-05-14 (Fri, 14 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll

  Log Message:
  -----------
  [AArch64][SVE] Add unpredicated vector BIC ISD node

Addition of this node allows us to better utilize the different forms of
the SVE BIC instructions, including using the alias to an AND (immediate).

Differential Revision: https://reviews.llvm.org/D101831