[all-commits] [llvm/llvm-project] ea0eec: IR+AArch64: add a "swiftasync" argument attribute.

[Tim Northover via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea0eec69f16e0f1b00fec413986e4e44f6f627fa
      https://github.com/llvm/llvm-project/commit/ea0eec69f16e0f1b00fec413986e4e44f6f627fa
  Author: Tim Northover <t.p.northover at gmail.com>
  Date:   2021-05-14 (Fri, 14 May 2021)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/AsmParser/LLToken.h
    M llvm/include/llvm/Bitcode/LLVMBitCodes.h
    M llvm/include/llvm/CodeGen/TargetCallingConv.h
    M llvm/include/llvm/CodeGen/TargetFrameLowering.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/IR/Attributes.td
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/Target/TargetCallingConv.td
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
    M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
    M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/IR/Attributes.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Target/AArch64/AArch64CallingConvention.td
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64FastISel.cpp
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64FrameLowering.h
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
    M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
    M llvm/lib/Transforms/Utils/CodeExtractor.cpp
    M llvm/test/Bitcode/attributes.ll
    M llvm/test/Bitcode/compatibility.ll
    A llvm/test/CodeGen/AArch64/swift-async-reg.ll
    A llvm/test/CodeGen/AArch64/swift-async-unwind.ll
    A llvm/test/CodeGen/AArch64/swift-async.ll
    A llvm/test/Verifier/swiftasync.ll

  Log Message:
  -----------
  IR+AArch64: add a "swiftasync" argument attribute.

This extends any frame record created in the function to include that
parameter, passed in X22.

The new record looks like [X22, FP, LR] in memory, and FP is stored with 0b0001
in bits 63:60 (CodeGen assumes they are 0b0000 in normal operation). The effect
of this is that tools walking the stack should expect to see one of three
values there:

  * 0b0000 => a normal, non-extended record with just [FP, LR]
  * 0b0001 => the extended record [X22, FP, LR]
  * 0b1111 => kernel space, and a non-extended record.

All other values are currently reserved.

If compiling for arm64e this context pointer is address-discriminated with the
discriminator 0xc31a and the DB (process-specific) key.

There is also an "i8** @llvm.swift.async.context.addr()" intrinsic providing
front-ends access to this slot (and forcing its creation initialized to nullptr
if necessary).