[all-commits] [llvm/llvm-project] 4789fc: AArch64: support i128 cmpxchg in GlobalISel.

[Tim Northover via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4789fc75d3501f14cfbd5b102f173721d498ff58
      https://github.com/llvm/llvm-project/commit/4789fc75d3501f14cfbd5b102f173721d498ff58
  Author: Tim Northover <t.p.northover at gmail.com>
  Date:   2021-05-14 (Fri, 14 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
    M llvm/lib/Target/AArch64/AArch64InstrGISel.td
    M llvm/lib/Target/AArch64/AArch64RegisterBanks.td
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
    A llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
    A llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir

  Log Message:
  -----------
  AArch64: support i128 cmpxchg in GlobalISel.

There are three essentially different cases to handle:

  * -O1, no LSE. The IR is expanded to ldxp/stxp and we need patterns to select
    them.
  * -O0, no LSE. We get G_ATOMIC_CMPXCHG, and need to produce CMP_SWAP_N
    pseudos. The registers are all 64-bit so this is easy.
  * LSE. We get G_ATOMIC_CMPXCHG and need to produce a CASP instruction with
    XSeqPair registers.

The last case is by far the hardest, and and adds 128-bit GPR support as a
byproduct.