[all-commits] [llvm/llvm-project] 6e6f9a: [AArch64][SVE] Improve sve.convert.to.svbool lowering

[Peter Waller via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e6f9a636b1917f366821fb0a5c37cde19634c7a
      https://github.com/llvm/llvm-project/commit/6e6f9a636b1917f366821fb0a5c37cde19634c7a
  Author: Peter Waller <peter.waller at arm.com>
  Date:   2021-05-12 (Wed, 12 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll

  Log Message:
  -----------
  [AArch64][SVE] Improve sve.convert.to.svbool lowering

The sve.convert.to.svbool lowering has the effect of widening a logical
<M x i1> vector representing lanes into a physical <16 x i1> vector
representing bits in a predicate register.

In general, if converting to svbool, the contents of lanes in the
physical register might not be known. For sve.convert.to.svbool the new
lanes are specified to be zeroed, requiring 'and' instructions to mask
off the new lanes. For lanes coming from a ptrue or a comparison,
however, they are known to be zero.

CodeGen Before:
  ptrue p0.s, vl16
  ptrue p1.s
  ptrue p2.b
  and   p0.b, p2/z, p0.b, p1.b
  ret

After:
  ptrue	p0.s, vl16
  ret

Differential Revision: https://reviews.llvm.org/D101544