[all-commits] [llvm/llvm-project] dc00cb: [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with s...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dc00cbb5053895356955a6dc03632d4fa05048e3
      https://github.com/llvm/llvm-project/commit/dc00cbb5053895356955a6dc03632d4fa05048e3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-05-11 (Tue, 11 May 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

  Log Message:
  -----------
  [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl.

Limited to splats because we would need to truncate the shift
amount vector otherwise.

I tried to do this with new ISD nodes and a DAG combine to
avoid such a large pattern, but we don't form the splat until
LegalizeDAG and need DAG combine to remove a scalable->fixed->scalable
cast before it becomes visible to the shift node. By the time that
happens we've already visited the truncate node and won't revisit it.

I think I have an idea how to improve i64 on RV32 I'll save for a
follow up.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D102019