[all-commits] [llvm/llvm-project] 49950c: [SLP] restrict matching of load combine candidates

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 49950cb1f6f699cbb9d8f141c0c043d4795c3417
      https://github.com/llvm/llvm-project/commit/49950cb1f6f699cbb9d8f141c0c043d4795c3417
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-05-11 (Tue, 11 May 2021)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/SLPVectorizer/AArch64/widen.ll

  Log Message:
  -----------
  [SLP] restrict matching of load combine candidates

The test example from https://llvm.org/PR50256 (and reduced here)
shows that we can match a load combine candidate even when there
are no "or" instructions. We can avoid that by confirming that we
do see an "or". This doesn't apply when matching an or-reduction
because that match begins from the operands of the reduction.

Differential Revision: https://reviews.llvm.org/D102074