[all-commits] [llvm/llvm-project] 635164: [AArch64][SVE] Improve SVE codegen for fixed lengt...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 635164b95a8e5d8c0c40804c7ffa3981a82b917a
      https://github.com/llvm/llvm-project/commit/635164b95a8e5d8c0c40804c7ffa3981a82b917a
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    A llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll

  Log Message:
  -----------
  [AArch64][SVE] Improve SVE codegen for fixed length BITCAST

Expanding a fixed length operation involves wrapping the operation in an
insert/extract subvector pair, as such, when this is done to bitcast we
end up with an extract_subvector of a bitcast. DAGCombine tries to
convert this into a bitcast of an extract_subvector which restores the
initial fixed length bitcast, causing an infinite loop of legalization.

As part of this patch, we must make sure the above DAGCombine does not
trigger after legalization if the created bitcast would not be legal.

Differential Revision: https://reviews.llvm.org/D101990