[all-commits] [llvm/llvm-project] 65c89c: [AArch64][SVE] Better utilisation of unpredicated ...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65c89cd1a62ad1f2e9b879edc10a806f13c21892
      https://github.com/llvm/llvm-project/commit/65c89cd1a62ad1f2e9b879edc10a806f13c21892
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-05-10 (Mon, 10 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
    A llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll
    A llvm/test/CodeGen/AArch64/sve2-intrinsics-int-arith-imm.ll

  Log Message:
  -----------
  [AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics

When using predicated intrinsics, if the predicate used is all lanes active,
use an unpredicated form of the instruction, additionally this allows for
better use of immediate forms.

This only includes instructions where the unpredicated/predicated forms
matched in such a way that instruction selection would not introduce extra
ptrue instructions. This allows us to convert the intrinsics directly to
architecture independent ISD nodes.

Depends on D101062

Differential Revision: https://reviews.llvm.org/D101828