[all-commits] [llvm/llvm-project] d54949: [NFCI][X86] Mark a few lately-added system instruc...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d5494931f2acd6a5b3ca349ed54813226b0c9040
      https://github.com/llvm/llvm-project/commit/d5494931f2acd6a5b3ca349ed54813226b0c9040
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-09 (Sun, 09 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrInfo.td
    M llvm/lib/Target/X86/X86InstrSystem.td

  Log Message:
  -----------
  [NFCI][X86] Mark a few lately-added system instructions as such for Scheduling purposes


  Commit: f8589292084b41fc70da93fb1e23bb576bd1f8f3
      https://github.com/llvm/llvm-project/commit/f8589292084b41fc70da93fb1e23bb576bd1f8f3
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-09 (Sun, 09 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver3.td

  Log Message:
  -----------
  [NFCI][X86] Mark Znver3 scheduling model as complete

To the best of my knowledge, all instructions are modelled,
and have reasonable values to them; flipping the switch
doesn't cause any diff for MCA tests, so either we're good,
or we have test coverage gaps.

I'm not really sure why no other X86 sched model is marked as complete.


  Commit: 4aec8f4ce0f564aa68c23b9e29c2e3a945eec947
      https://github.com/llvm/llvm-project/commit/4aec8f4ce0f564aa68c23b9e29c2e3a945eec947
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-09 (Sun, 09 May 2021)

  Changed paths:
    A llvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero-cost.ll
    A llvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero-debuginfo.ll
    A llvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero.ll

  Log Message:
  -----------
  [NFC][LoopIdiom] Add some tests for 'lshr until zero' ('count active bits') "on steroids" idiom


Compare: https://github.com/llvm/llvm-project/compare/492173d42b32...4aec8f4ce0f5