[all-commits] [llvm/llvm-project] 808bc1: [GlobalISel] Don't form zero/sign extending loads ...

[Amara Emerson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 808bc11d9e1aa01edaf7ec4e56be3aee5ed42a83
      https://github.com/llvm/llvm-project/commit/808bc11d9e1aa01edaf7ec4e56be3aee5ed42a83
  Author: Amara Emerson <amara at apple.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir

  Log Message:
  -----------
  [GlobalISel] Don't form zero/sign extending loads for atomics.

For importing patterns, we only support matching G_LOAD, not G_ZEXTLOAD or
G_SEXTLOAD.

Differential Revision: https://reviews.llvm.org/D101932