[all-commits] [llvm/llvm-project] e6d688: [NFC][X86][MCA] Increase iteration count in reg mo...

Fri May 7 07:07:32 PDT 2021

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e6d688ec96706c1bbcb27419333828ec61752fab
      https://github.com/llvm/llvm-project/commit/e6d688ec96706c1bbcb27419333828ec61752fab
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-mmx.s

  Log Message:
  -----------
  [NFC][X86][MCA] Increase iteration count in reg move elimination tests

So the IPC actually stabilizes at 6.

  Commit: c3cd8ed0097b07e5454255ffe5899ded21ca0bff
      https://github.com/llvm/llvm-project/commit/c3cd8ed0097b07e5454255ffe5899ded21ca0bff
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver3.td

  Log Message:
  -----------
  [NFC][X86] AMD Zen 3: move sched classes for renameables moves togeter

  Commit: d8c6202576771f0e1478b3abdd246600caf7d704
      https://github.com/llvm/llvm-project/commit/d8c6202576771f0e1478b3abdd246600caf7d704
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver3.td
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s

  Log Message:
  -----------
  [X86] AMD Zen 3: throughput for renameable GPR moves is 6

They are resolved at the register rename stage without
using any execution units.

  Commit: cbabe4f4d62a6bcee206e0673de559805a092420
      https://github.com/llvm/llvm-project/commit/cbabe4f4d62a6bcee206e0673de559805a092420
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    A llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-sse-xmm.s

  Log Message:
  -----------
  [NFC][X86][MCA] AMD Zen 3: Add tests for renameable SSE XMM moves

  Commit: bcbfc22ff9b2f16d77489b0ce34e8d96e4f9ae5b
      https://github.com/llvm/llvm-project/commit/bcbfc22ff9b2f16d77489b0ce34e8d96e4f9ae5b
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    A llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-xmm.s

  Log Message:
  -----------
  [NFC][X86][MCA] AMD Zen 3: Add tests for renameable AVX XMM moves

  Commit: 0d961fbd525cb7df3e981d6469b81cbf8f5e5883
      https://github.com/llvm/llvm-project/commit/0d961fbd525cb7df3e981d6469b81cbf8f5e5883
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    A llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-ymm.s

  Log Message:
  -----------
  [NFC][X86][MCA] AMD Zen 3: Add tests for renameable AVX YMM moves

  Commit: 9db4203883f57f34e7e88fd6deb761ef8a9f7d5a
      https://github.com/llvm/llvm-project/commit/9db4203883f57f34e7e88fd6deb761ef8a9f7d5a
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver3.td
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-sse-xmm.s

  Log Message:
  -----------
  [X86] AMD Zen 3: SSE XMM moves are zero-cycle

I've verified this with llvm-exegesis.
This is not limited to zero registers.

Refs:
AMD SOG 19h, 2.9.4 Zero Cycle Move
The processor is able to execute certain register to register
mov operations with zero cycle delay.

Agner,
22.13 Instructions with no latency
Register-to-register move instructions are resolved at
the register rename stage without using any execution units.
These instructions have zero latency. It is possible to do six such
register renamings per clock cycle, and it is even possible to
rename the same register multiple times in one clock cycle.

  Commit: ee020b930d1299acf42b759dd15a44d2020ef963
      https://github.com/llvm/llvm-project/commit/ee020b930d1299acf42b759dd15a44d2020ef963
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver3.td
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-xmm.s

  Log Message:
  -----------
  [X86] AMD Zen 3: AVX XMM moves are zero-cycle

I've verified this with llvm-exegesis.
This is not limited to zero registers.

  Commit: 715c0d0bd412141e0404d5bfcad4dddac3bfc0d0
      https://github.com/llvm/llvm-project/commit/715c0d0bd412141e0404d5bfcad4dddac3bfc0d0
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver3.td
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-ymm.s

  Log Message:
  -----------
  [X86] AMD Zen 3: AVX YMM moves are zero-cycle

I've verified this with llvm-exegesis.
This is not limited to zero registers.

  Commit: 758c173309edbd6ac3958eb08dc01b6524badff8
      https://github.com/llvm/llvm-project/commit/758c173309edbd6ac3958eb08dc01b6524badff8
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver3.td
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-xmm.s
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-ymm.s
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-sse-xmm.s
    M llvm/test/tools/llvm-mca/X86/Znver3/resources-avx1.s
    M llvm/test/tools/llvm-mca/X86/Znver3/resources-sse1.s
    M llvm/test/tools/llvm-mca/X86/Znver3/resources-sse2.s

  Log Message:
  -----------
  [X86] AMD Zen 3: throughput for renameable XMM/YMM moves is 6

They are resolved at the register rename stage without
using any execution units.

  Commit: 34de155f7e335e9e69276356565dcc31ed7d8535
      https://github.com/llvm/llvm-project/commit/34de155f7e335e9e69276356565dcc31ed7d8535
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-05-07 (Fri, 07 May 2021)

  Changed paths:
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-xmm.s
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-ymm.s
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-mmx.s
    M llvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-sse-xmm.s

  Log Message:
  -----------
  [NFC][X86][MCA] AMD Zen3 Decrease iteration count in reg-move-elimination tests

Drop it just enough so it still produces the right IPC.

Compare: https://github.com/llvm/llvm-project/compare/f42355e17c3f...34de155f7e33