[all-commits] [llvm/llvm-project] b856f4: [ARM] Transforming memcpy to Tail predicated Loop

[malJaj via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b856f4a232cbd43476e9b9f75c80aacfc6f5c152
      https://github.com/llvm/llvm-project/commit/b856f4a232cbd43476e9b9f75c80aacfc6f5c152
  Author: Malhar Jajoo <malhar.jajoo at arm.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
    M llvm/lib/Target/ARM/ARMSubtarget.h
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
    A llvm/test/CodeGen/Thumb2/mve-tp-loop.ll
    A llvm/test/CodeGen/Thumb2/mve-tp-loop.mir

  Log Message:
  -----------
  [ARM] Transforming memcpy to Tail predicated Loop

This patch converts llvm.memcpy intrinsic into Tail Predicated
Hardware loops for a target that supports the Arm M-profile
Vector Extension (MVE).

>From an implementation point of view, the patch

- adds an ARM specific SDAG Node (to which the llvm.memcpy intrinsic is lowered to, during first phase of ISel)
- adds a corresponding TableGen entry to generate a pseudo instruction, with a custom inserter,
  on matching the above node.
- Adds a custom inserter function that expands the pseudo instruction into MIR suitable
   to be (by later passes) into a WLSTP loop.

Note: A cli option is used to control the conversion of memcpy to TP
loop and this option is currently disabled by default. It may be enabled
in the future after further downstream testing.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D99723