[all-commits] [llvm/llvm-project] fa0b93: GlobalISel: Use DAG call lowering infrastructure i...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed May 5 14:35:23 PDT 2021 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fa0b93b5a0866aad3ce517daab6cd91cc67823ad
      https://github.com/llvm/llvm-project/commit/fa0b93b5a0866aad3ce517daab6cd91cc67823ad
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-05-05 (Wed, 05 May 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
    M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/ARM/ARMCallLowering.cpp
    M llvm/lib/Target/X86/X86CallLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
    M llvm/test/CodeGen/X86/GlobalISel/add-scalar.ll
    M llvm/test/CodeGen/X86/GlobalISel/callingconv.ll
    M llvm/test/CodeGen/X86/GlobalISel/ext.ll
    M llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
    M llvm/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll

  Log Message:
  -----------
  GlobalISel: Use DAG call lowering infrastructure in a more compatible way

Unfortunately the current call lowering code is built on top of the
legacy MVT/DAG based code. However, GlobalISel was not using it the
same way. In short, the DAG passes legalized types to the assignment
function, and GlobalISel was passing the original raw type if it was
simple.

I do believe the DAG lowering is conceptually broken since it requires
picking a type up front before knowing how/where the value will be
passed. This ends up being a problem for AArch64, which wants to pass
i1/i8/i16 values as a different size if passed on the stack or in
registers.

The argument type decision is split across 3 different places which is
hard to follow. SelectionDAG builder uses
getRegisterTypeForCallingConv to pick a legal type, tablegen gives the
illusion of controlling the type, and the target may have additional
hacks in the C++ part of the call lowering. AArch64 hacks around this
by not using the standard AnalyzeFormalArguments and special casing
i1/i8/i16 by looking at the underlying type of the original IR
argument.

I believe people have generally assumed the calling convention code is
processing the original types, and I've discovered a number of dead
paths in several targets.

x86 actually relies on the opposite behavior from AArch64, and relies
on x86_32 and x86_64 sharing calling convention code where the 64-bit
cases implicitly do not work on x86_32 due to using the pre-legalized
types.

AMDGPU targets without legal i16/f16 have always used a broken ABI
that promotes to i32/f32. GlobalISel accidentally fixed this to be the
ABI we should have, but this fixes it so we're using the worse ABI
that is compatible with the DAG. Ideally we would fix the DAG to match
the old GlobalISel behavior, but I don't wish to fight that battle.

A new native GlobalISel call lowering framework should let the target
process the incoming types directly.

CCValAssigns select a "ValVT" and "LocVT" but the meanings of these
aren't entirely clear. Different targets don't use them consistently,
even within their own call lowering code. My current belief is the
intent was "ValVT" is supposed to be the legalized value type to use
in the end, and and LocVT was supposed to be the ABI passed type
(which is also legalized).

With the default CCState::Analyze functions always passing the same
type for these arguments, these only differ when the TableGen part of
the lowering decide to promote the type from one legal type to
another. AArch64's i1/i8/i16 hack ends up inverting the meanings of
these values, so I had to add an additional hack to let the target
interpret how large the argument memory is.

Since targets don't consistently interpret ValVT and LocVT, this
doesn't produce quite equivalent code to the initial DAG
lowerings. I've opted to consistently interpret LocVT as the in-memory
size for stack passed values, and ValVT as the register type to assign
from that memory. We therefore produce extending loads directly out of
the IRTranslator, whereas the DAG would emit regular loads of smaller
values. This will also produce loads/stores that are wider than the
argument value if the allocated stack slot is larger (and there will
be undef padding bytes). If we had the optimizations to reduce
load/stores based on truncated values, this wouldn't produce a
different end result.

Since ValVT/LocVT are more consistently interpreted, we now will emit
more G_BITCASTS as requested by the CCAssignFn. For example AArch64
was directly assigning types to some physical vector registers which
according to the tablegen spec should have been casted to a vector
with a different element type.

This also moves the responsibility for inserting
G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the
generic code, which is closer to how SelectionDAGBuilder works.

I had to xfail an x86 test since I don't see a quick way to fix it
right now (I filed bug 50035 for this). It's broken independently of
this change, and only triggers since now we end up with more ands
which hit the improperly handled selection pattern.

I also observed that FP arguments that need promotion (e.g. f16 passed
as f32) are broken, and use regular G_TRUNC and G_ANYEXT.

TLDR; the current call lowering infrastructure is bad and nobody has
ever understood how it chooses types.


  Commit: 23ae35e858da37c753b8efaac965046358ec3818
      https://github.com/llvm/llvm-project/commit/23ae35e858da37c753b8efaac965046358ec3818
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-05-05 (Wed, 05 May 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86CallLowering.cpp
    M llvm/lib/Target/X86/X86CallLowering.h
    M llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

  Log Message:
  -----------
  X86/GlobalISel: Use generic version of splitToValueTypes

The custom insert of an unmerge and the callback weirdness should be
unnecessary. Since handleAssignments should now use
getRegisterTypeForCalling conv as SelectionDAG builder would, this
should now just be able to use the generic code. X86-32 relies on the
generated CCAssignFns not seeing illegal types and sharing code with
x86_64, so i64 values would incorrectly be assigned to 64-bit
registers.


  Commit: 8fc4eb9e732006b3b4f0b224c79ab097f3026f85
      https://github.com/llvm/llvm-project/commit/8fc4eb9e732006b3b4f0b224c79ab097f3026f85
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-05-05 (Wed, 05 May 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

  Log Message:
  -----------
  AMDGPU/GlobalISel: Remove unnecessary override

This is the same as the default implementation


  Commit: e723b511e6e951444d2a646a23fc2e9cf4faecd4
      https://github.com/llvm/llvm-project/commit/e723b511e6e951444d2a646a23fc2e9cf4faecd4
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-05-05 (Wed, 05 May 2021)

  Changed paths:
    M llvm/docs/GlobalISel/IRTranslator.rst

  Log Message:
  -----------
  GlobalISel: Update documentation


Compare: https://github.com/llvm/llvm-project/compare/0edc4bc84aa2...e723b511e6e9

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