[all-commits] [llvm/llvm-project] 1ee50b: [AArch64] Fix scalar imm variants of SIMD shift le...

[Andrew Savonichev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ee50b473168735752a2f80ae9b356cfa70a76d0
      https://github.com/llvm/llvm-project/commit/1ee50b473168735752a2f80ae9b356cfa70a76d0
  Author: Andrew Savonichev <andrew.savonichev at gmail.com>
  Date:   2021-05-05 (Wed, 05 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll

  Log Message:
  -----------
  [AArch64] Fix scalar imm variants of SIMD shift left instructions

This issue was reported in PR50057: Cannot select:
t10: i64 = AArch64ISD::VSHL t2, Constant:i32<2>

Shift intrinsics (llvm.aarch64.neon.ushl.i64 and sshl) with a constant
shift operand are lowered into AArch64ISD::VSHL in tryCombineShiftImm.
VSHL has i64 and v1i64 patterns for a right shift, but only v1i64 for
a left shift.

This patch adds the missing i64 pattern for AArch64ISD::VSHL, and LIT
tests to cover scalar variants (i64 and v1i64) of all shift
intrinsics (only ushl and sshl cases fail without the patch, others
were just not covered).

Differential Revision: https://reviews.llvm.org/D101580