[all-commits] [llvm/llvm-project] 6a1760: [AMDGPU] Disable the scalar IR, SDWA and load stor...

[bsaleil via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a17609157196878b9cd9aa9ce71bde247ca14db
      https://github.com/llvm/llvm-project/commit/6a17609157196878b9cd9aa9ce71bde247ca14db
  Author: Baptiste Saleil <baptiste.saleil at amd.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    A llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

  Log Message:
  -----------
  [AMDGPU] Disable the scalar IR, SDWA and load store vectorizer passes at -O1

This patch disables some of the passes at -O1. These passes have a significant
impact on compilation time, so we only want them to be enabled starting from -O2.

Differential Revision: https://reviews.llvm.org/D101414