[all-commits] [llvm/llvm-project] 8a40bf: [AArch64][SVE] More unpredicated ld1/st1 patterns ...

[Eli Friedman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8a40bf6d210fd2b5180841579d412826c381fb2b
      https://github.com/llvm/llvm-project/commit/8a40bf6d210fd2b5180841579d412826c381fb2b
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2021-05-03 (Mon, 03 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll

  Log Message:
  -----------
  [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes

In some cases, we can improve the generated code by using a load with
the "wrong" element width: in particular, using ld1b/st1b when we see
reg+reg without a shift.

Differential Revision: https://reviews.llvm.org/D100527