[all-commits] [llvm/llvm-project] 753185: [CodeGen][ARM] Implement atomicrmw as pseudo opera...

[tmatheson-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 753185031d939711f8733639a77a6fdc3bdbad22
      https://github.com/llvm/llvm-project/commit/753185031d939711f8733639a77a6fdc3bdbad22
  Author: Tomas Matheson <tomas.matheson at arm.com>
  Date:   2021-05-03 (Mon, 03 May 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    A llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_all.ll
    M llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll

  Log Message:
  -----------
  [CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0

atomicrmw instructions are expanded by AtomicExpandPass before register allocation
into cmpxchg loops. Register allocation can insert spills between the exclusive loads
and stores, which invalidates the exclusive monitor and can lead to infinite loops.

To avoid this, reimplement atomicrmw operations as pseudo-instructions and expand them
after register allocation.

Floating point legalisation:
f16 ATOMIC_LOAD_FADD(*f16, f16) is legalised to
f32 ATOMIC_LOAD_FADD(*i16, f32) and then eventually
f32 ATOMIC_LOAD_FADD_16(*i16, f32)

Differential Revision: https://reviews.llvm.org/D101164

Originally submitted as 3338290c187b254ad071f4b9cbf2ddb2623cefc0.
Reverted in c7df6b1223d88dfd15248fbf7b7b83dacad22ae3.