[all-commits] [llvm/llvm-project] 1b24f3: [InstCombine] improve demanded bits analysis of le...

[RotateRight via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1b24f35f843cd58ea22ec3968d0d2589c5bdc2c9
      https://github.com/llvm/llvm-project/commit/1b24f35f843cd58ea22ec3968d0d2589c5bdc2c9
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-05-03 (Mon, 03 May 2021)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/rotate.ll
    M llvm/test/Transforms/InstCombine/shl-demand.ll

  Log Message:
  -----------
  [InstCombine] improve demanded bits analysis of left-shifted operand

If we don't demand high bits, then we also don't care about those
high bits of a left-shift operand regardless of shift amount.
I noticed the sext/trunc pattern in a motivating example.
It seems like there should be a low-bits with right-shift sibling,
but I haven't looked at that yet.

https://alive2.llvm.org/ce/z/JuS6jc
https://rise4fun.com/Alive/Trm (not sure how to use 'width' with Alive1)
https://alive2.llvm.org/ce/z/gRadbF

Differential Revision: https://reviews.llvm.org/D101489