[all-commits] [llvm/llvm-project] 643043: [TableGen] Use sign rotated VBR for OPC_EmitInteger.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6430430958928099cf38afe588000dcff2b3fb0b
      https://github.com/llvm/llvm-project/commit/6430430958928099cf38afe588000dcff2b3fb0b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-05-02 (Sun, 02 May 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAGISel.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    M llvm/test/TableGen/DAGDefaultOps.td
    M llvm/test/TableGen/dag-isel-regclass-emit-enum.td
    M llvm/test/TableGen/dag-isel-subregs.td
    M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp

  Log Message:
  -----------
  [TableGen] Use sign rotated VBR for OPC_EmitInteger.

This allows for a much more efficient encoding for small negative
numbers by storing the sign bit first and negating the rest of
the bits. This was already being used for OPC_CheckInteger.

For every in tree target this affects, the table got smaller.
R600GenDAGISel.inc saw the largest reduction of 7K.

I did have to add a new opcode for StringIntegers used for
register class ids and subregister indices since we don't have the
integer value to encode. The enum name is emitted directly into
the table. Previously assumed the enum would expand to a positive
7-bit number. We might be able to just shift that right by 1 and
assume it is a positive 6 bit number, but that will need more
investigation.