[all-commits] [llvm/llvm-project] 4751ca: [AArch64] Prevent spilling between ldxr/stxr pairs

[LemonBoy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4751cadcca45984d7671e594ce95aed8fe030bf1
      https://github.com/llvm/llvm-project/commit/4751cadcca45984d7671e594ce95aed8fe030bf1
  Author: LemonBoy <thatlemon at gmail.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
    A llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
    M llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll

  Log Message:
  -----------
  [AArch64] Prevent spilling between ldxr/stxr pairs

Apply the same logic used to check if CMPXCHG nodes should be expanded
at -O0: the register allocator may end up spilling some register in
between the atomic load/store pairs, breaking the atomicity and possibly
stalling the execution.

Fixes PR48017

Reviewed By: efriedman

Differential Revision: https://reviews.llvm.org/D101163