[all-commits] [llvm/llvm-project] 936c77: [AArch64] Adds a pre-indexed paired Load/Store opt...

[Stelios Ioannou via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 936c777e2bf86cd78b532c1331c4f7ee90b95383
      https://github.com/llvm/llvm-project/commit/936c777e2bf86cd78b532c1331c4f7ee90b95383
  Author: Stelios Ioannou <stelios.ioannou at arm.com>
  Date:   2021-04-30 (Fri, 30 Apr 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
    M llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
    A llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
    A llvm/test/CodeGen/AArch64/strpre-str-merge.mir

  Log Message:
  -----------
  [AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR.

This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and
LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single
STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively.
For each pair, there is a MIR test that verifies this optimization.

Differential Revision: https://reviews.llvm.org/D99272

Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7